1. Field of the Invention
The present invention relates generally to a semiconductor memory system, particularly to a cache memory system having error correcting means contained therein.
2. Description of the Prior Art
In recent years, capacity of a semiconductor memory device is increased. Correspondingly, there occurs some problems. For example, soft errors are caused. Soft errors means that information stored in a memory cell erroneously changes. One of the causes of soft errors is incidence of alpha articles, which is a main problem to be considered in a recent dynamic random access memory (referred to as dynamic RAM hereinafter). More particularly, soft errors are caused, for example, upon incidence of alpha particles generated by radioactive substances included in package materials or the like. The soft errors return to the normal state by rewriting. Thus, soft errors are not a permanent failure. The frequency of soft errors becomes high particularly in a high density dynamic random access memory (RAM). In order to solve the soft error problem, a semiconductor memory device having an error correcting circuit contained therein is proposed, which is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 2300/1984.
FIG. 1 is a block diagram showing structure of a conventional semiconductor memory device having an error correcting circuit contained therein.
Referring to FIG. 1, a memory cell array 1 comprises a plurality of memory cells arranged in a plurality of rows and columns. The memory cell array 1 is divided into a plurality of blocks, each of the blocks comprising memory cells arranged in a plurality of columns. The memory cell array 1 shown in FIG. 1 is divided into four blocks B1 to B4, each of the blocks B1 to B4 comprising memory cells arranged in (m+k) columns. (m+k)-bit data comprising information bits including m bits and check bits including k bits are stored as one word data in each row of each of the blocks in the memory cell array 1.
The memory cell array 1 is provided with a row decoder 2 responsive to a row address signal RA for selecting one row of the memory cell array 1 and a block decoder 3 responsive to a block selecting signal BK for selecting one block in the memory cell array 1. A row address buffer 4 suitably applies to the row decoder 2 the row address signal RA applied to a row address input terminal 5. A column address buffer 6 applies to the block decoder 3 a part of a column address signal CA applied to a column address input terminal 7 as a block selecting signal BK and applies to a 1/m decoder 11 as described below the remainder of the column address signal CA as a bit selecting signal BI.
Furthermore, a check bit generating circuit 8, an error correcting circuit 9 and a register 10 are connected to the memory cell array 1. The check bit generating circuit 8 generates check bits including k bits for detecting and correcting an error in both information bits including m bits and the check bits or an error in information bits. The error correcting circuit 9 is responsive to the check bits for detecting an error in both the information bits and the check bits or an error in the information bits and correcting the detected error. One word data is temporarily stored in the register 10. The 1/m decoder 11 is responsive to the bit selecting signal BI applied from the column address buffer 6 for selecting one bit of information bits including m bits and providing the same to a data input/output terminal 12 or for applying to any one bit in the register 10 one bit data to be applied to the data input/output terminal 12.
Description is now made of operation of the semiconductor memory device having an error correcting circuit contained therein.
At the time of reading out data, when one bit in the memory cell array 1 is accessed by the row address signal RA and the column address signal CA, one word data including the one bit is selected by the row decoder 2 and the block decoder 3 and transferred to the error correcting circuit 9. The error correcting circuit 9 is responsive to check bits including k bits included in the one word data for detecting the presence or absence of an error of information bits including m bits. If an error is detected, the error correcting circuit 9 corrects the error and transfers the same to the 1/m decoder 11. The 1/m decoder 11 is responsive to the bit selecting signal BI applied from the column address buffer 6 for selecting one bit of the information bits including m bits and providing the same to the data input/output terminal 12.
At the time of writing data, when one bit in the memory cell array 1 is accessed by the row address signal RA and the column address signal CA, one word data including the one bit is selected by the row decoder 2 and the block decoder 3 and transferred to the register 10. The 1/m decoder 11 is responsive to the bit selecting signal BI applied from the column address buffer 6 for transferring to any one bit in the register 10 one bit data to be applied to the data input/output terminal 12. Therefore, one bit of information bits of data stored in the register 10 is reloaded. The information bits including the reloaded bit is transferred to one row in a block selected by the row decoder 2 and the block decoder 3 and also transferred to the check bit generating circuit 8. The check bit generating circuit 8 is responsive to information bits including m bits for generating check bits including k bits. The check bits are transferred to the same row in the same block as that including the corresponding information bits.
In addition to the above described Gazette, a semiconductor memory device having an error correcting circuit contained therein is described in, for example, IEEE Journal of Solid-State Circuits, Vol. SC-19, Oct. 1984, pp. 627-633 and IEEE Journal of Solid-State Circuits, Vol. SC-20, Oct. 1985, pp. 958-963. In addition, an error correcting code is described in IBM J. RES. DEVELOP, Vol. 28, No. 2, Mar. 1984, pp. 124-134.
Description is now made of an example of the fundamental principle of a method for generating check bits and a method for correcting an error.
Referring to FIG. 2A, information bits including 16 bits are arranged in a 4 by 4 matrix. When the sum of a bits in one row is an even-number, "0" is arranged at the right of the row. When the sum of bits in one row is an odd-number, "1" is arranged at the right of the row. In addition, when the sum of bits in one column is an even-number, "0" is arranged under the column. When the sum of bits in one column is an odd-number, "1" is arranged under the column. Therefore, bits arranged at the right of and under the information bits in a matrix serve as check bits.
For example, as shown in FIG. 2B, it is assumed that a bit at an intersection of the third row and the third column changes from "1" to "0". In this case, since the sum of bits in the third row is an odd-number, the check bit must be "1" if there is no error in this row. However, since the check bit is "0", any bit in this row is erroneous. In addition, since the sum of bits in the third column is an odd-number, the check bit must be "1" if there is no error in the column. However, since the check bit is "0", any bit in the column is erroneous. As a result, it is determined that a bit at an intersection of the third row and the third column is erroneous. Thus, this bit is inverted from "0" to "1" so that the error is corrected.
In the above described conventional semiconductor memory device, since data is passed through the error correcting circuit 9 at the time of reading out data and the data is passed through the check bit generating circuit 8 at the time of writing data, the access time and the cycle time are increased. For example, when the error correcting circuit 9 is added to a dynamic RAM having an access time of 100 ns, the access time increases by approximately 20 ns.